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ADVANCE INFORMATION
CRYSTAL-TO-MLVDS PCI EXPRESSTM CLOCK SYNTHESIZER W/SPREAD SPECTRUM
ICS845204
General Description
The ICS845204 is a 4 output PCI Express clock synthesizer optimized to generate low jitter PCI HiPerClockSTM ExpressTM reference clocks with or without spread spectrum modulation and is a member of the HiPerClockSTM family of high performance clock solutions from IDT. Spread type and amount can be configured via the SSC control pins. Using a 25MHz, 18pF parallel resonant crystal, the device will generate M-LVDS clocks at either 25MHz, 100MHz, 125MHz or 250MHz. The ICS845204 uses a low jitter VCO that easily meets PCI Express jitter requirements and is packaged in a 32-pin VFQFN package.
Features
* * * * * * * * * * *
Four differential spread spectrum clock outputs Each output can be individually disabled by separate output-enable inputs Crystal oscillator interface designed for 18pF, 25MHz parallel resonant crystal Supports the following output frequencies: 25MHz, 100MHz, 125MHz or 250MHz VCO range: 250MHz - 700MHz Supports SSC downspread at 0.05% and -0.75%, centerspread at 0.25% and no spread options Cycle-to-cycle jitter: 50ps (maximum) design target Period jitter, RMS: TBD Full 3.3V output supply mode 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
ICS
Pin Assignment
GND VDDA OE1
32 31 30 29 28 27 26 25 OE0 VDD nQ3 Q3 VDDO nc FSEL0 nc 1 2 3 4 5 6 7 8 9
FSEL1
nQ1
nQ0
Q0
nc
Q1
24 23 22 21 20 19 18 17 10 11 12 13 14 15 16
XTAL_OUT OE2 SSC0 XTAL_IN GND OE3 VDD
nc nc GND Q2 nQ2 SSC1 nc GND
ICS845204 32 Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
Block Diagram
00
25MHz
PLL Bypass
Q0 nQ0
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
250-700MHz
01 10 11
/5 /4 /2
Pullup OE0
Q1 nQ1
Pullup OE1
Feedback Divider /20
Q2 nQ2
Pullup OE2
SSC[1:0] Pullup:Pullup
Default = 100MHz Pulldown:Pullup
2
Spread Spectrum Control
Q3 nQ3
Pullup OE3
2
FSEL[1:0]
The Advance Information presented herein represents a product that is developmental or prototype. The noted characteristics are design targets. Integrated Device Technologies, Inc. (IDT) reserves the right to change any circuitry or specifications without notice.
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ADVANCE INFORMATION
Table 1. Pin Descriptions
Number 1 2, 11 3, 4 5 6, 8, 18, 23, 24, 27 7 9 10, 19 12 13, 14 15 16, 17, 22, 30 20, 21 25, 26 28 29 31, 32 Name OE0 VDD nQ3, Q3 VDDO nc FSEL0 FSEL1 SSC0, SSC1 OE3 XTAL_IN XTAL_OUT OE2 GND nQ2, Q2 nQ1, Q1 VDDA OE1 nQ0, Q0 Input Power Output Power Unused Input Input Input Input Input Input Power Output Output Power Input Output Pullup Pullup Pullup Pulldown Pullup Pullup Type Pullup Description Output enable pin for Q0/nQ0 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. Core supply pins. Differential output pair. M-LVDS interface levels. Output supply pin. No connect. Output frequency select pins. See Table 3A. LVCMOS/LVTTL interface levels. Output frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels. Spread spectrum control pins. See Table 3B. LVCMOS/LVTTL interface levels. Output enable pin for Q3/nQ3 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Output enable pin for Q2/nQ2 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. Power supply ground. Differential output pair. M-LVDS interface levels. Differential output pair. M-LVDS interface levels. Analog supply pin. Output enable pin for Q1/nQ1 outputs. Logic High, outputs are enabled. Logic LOW, outputs are in Hi-Z. LVCMOS/LVTTL interface levels. Differential output pair. M-LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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ADVANCE INFORMATION
Function Tables
Table 3A. F_SEL[1:0] Function Table
Inputs FSEL1 0 0 1 1 FSEL0 0 1 0 1 Outputs Q[0:3]/nQ[0:3] PLL Bypass (25MHz) 100MHz (default) 125MHz 250MHz SSC1 0 0 1 1
Table 3B. SSC[1:0] Function Table
Inputs SSC0 0 1 0 1 Center -0.25 Down -0.5 Down -0.75 No Spread (default) Spread%
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 42.4C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Power Supply Current Test Conditions Minimum 3.135 VDD - IDDA*10 3.135 Typical 3.3 3.3 3.3 TBD TBD TBD Maximum 3.465 VDD 3.465 Units V V V mA mA mA
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ADVANCE INFORMATION
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage F_SEL1 Input High Current SSC0, SSC1, FSEL0, OE0:OE3 F_SEL1 IIL Input Low Current SSC0, SSC1, FSEL0, OE0:OE3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
Table 4C. M-LVDS DC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70C
Symbol VOD VOD VOS VOS ISC Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Output Short Circuit Current 0.30 50 43 Test Conditions Minimum 480 50 2.10 Typical Maximum 650 Units mV mV V mV mA
Table 5. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Fundamental 25 50 7 TBD MHz Maximum Units
pF mW
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ADVANCE INFORMATION
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0C to 70
Parameter Symbol fOUT Output Frequency 25MHz, Integration Range: 12kHz - 20MHz 100MHz, Integration Range: 12kHz - 20MHz 125MHz, Integration Range: 12kHz - 20MHz 250MHz, Integration Range: 12kHz - 20MHz 25MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2 100MHz 125MHz 250MHz tsk(o) FXTAL FM FMF SSCRED tSTABLE tR / tF odc Output Skew; NOTE 2, 3 Crystal Input Range: NOTE 1 SSC Modulation Frequency; NOTE 4 SSC Modulation Factor; NOTE 4 Spectral Reduction Power-up Stable Clock Output Output Rise/Fall Time Output Duty Cycle 20% to 80% TBD 50 TBD 25 TBD TBD TBD 10 Test Conditions Minimum Typical Maximum 25 100 125 TBD TBD TBD TBD 50 50 50 50 Units MHz MHz MHz ps ps ps ps ps ps ps ps ps MHz kHz % dB ms ps %
tjit(per)
Period Jitter, Random
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Only valid within the VCO operating range. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Spread Spectrum clocking enabled.
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ADVANCE INFORMATION
Parameter Measurement Information
VOH VREF
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD, VDDO
Qx
VDDA
M-LVDS
nQx
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
VOL
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
-
-
3.3V LVDS Output Load AC Test Circuit
Period Jitter
nQx Qx nQy Qy
nQx Qx
tcycle n
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
tsk(o)
Output Skew
Cycle-to-Cycle Jitter
nQ0:nQ3
80% Clock Outputs
80% VOD
Q0:Q3
t PW
t
PERIOD
20% tR tF
20% odc = t PW t PERIOD x 100%
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
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ADVANCE INFORMATION
Parameter Measurement Information, continued
VDD VDD out
DC Input
M-LVDS
out
VOS/ VOS
DC Input
M-LVDS
100
100
VOD/ VOD out
Offset Voltage Setup
Differential Output Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS845204 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs:
M-LVDS Outputs
All unused M-LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached.
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ADVANCE INFORMATION
Crystal Input Interface
The ICS845204 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1
X1 18pF Parallel Crystal XTAL_OUT C2
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
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ADVANCE INFORMATION
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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ADVANCE INFORMATION
3.3V M-LVDS Driver Termination
A general M-LVDS interface is shown in Figure 5 In a 100 differential transmission line environment, M-LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple M-LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R2 100 50 R1 100
+
-
100 Differential Transmission Line
Figure 5. Typical M-LVDS Driver Termination
Reliability Information
Table 7. JA vs. Air Flow Table for a 32Lead VFQFN
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 42.4C/W 1 37.0C/W 2.5 33.2C/W
Transistor Count
The transistor count for ICS845204 is: 3749
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Package Outline and Package Dimension
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L
(N -1)x e
(R ef.)
N &N Even N 1 2
e (Ty p.) 2 If N & N
are Even (N -1)x e
OR
To p View
E2
E2 2
(Re f.)
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout
of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.
Table 8. Package Dimensions
JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220
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ADVANCE INFORMATION
Ordering Information
Table 9. Ordering Information
Part/Order Number 845204AK 845204AKT 845204AKLF 845204AKLFT Marking TBD TBD ICS845204AL ICS845204AL Package 32 Lead VFQFN 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Tray 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ADVANCE INFORMATION
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Corporate Headquarters
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Asia Pacific and Japan
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www.IDT.com
(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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